degré d"effort requis - significado y definición. Qué es degré d"effort requis
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Qué (quién) es degré d"effort requis - definición

STRAIGHTFORWARD TECHNIQUE USED TO ESTIMATE DELAY IN A CMOS CIRCUIT
Principle of logical effort; Branching Effort; Electrical Effort; Stage Effort

best effort         
PROVISION OF A SERVICE WITH NO QUALITY OF SERVICE GUARANTEE (E.G. COMPUTER NETWORKS, POSTAL SERVICES)
Best effort; Best-effort; Best Effort; Best-effort service; Best-effort network; Best effort delivery
<networking> A classification of low priority network traffic, used especially the Internet. Different kinds of traffic have different priorities. Videoconferencing and other types of real-time communication, for example, require a certain minimum guaranteed bandwidth and latency and so must be given a high priority. Electronic mail, on the other hand, can tolerate an arbitrarily long delay and is classified as a "best-effort" service. [Scientific American, Nov. 1994, pp. 83-84]. (1995-04-04)
Best-effort delivery         
PROVISION OF A SERVICE WITH NO QUALITY OF SERVICE GUARANTEE (E.G. COMPUTER NETWORKS, POSTAL SERVICES)
Best effort; Best-effort; Best Effort; Best-effort service; Best-effort network; Best effort delivery
Best-effort delivery describes a network service in which the network does not provide any guarantee that data is delivered or that delivery meets any quality of service. In a best-effort network, all users obtain best-effort service.
effort         
WIKIMEDIA DISAMBIGUATION PAGE
Effort (disambiguation)
¦ noun
1. a vigorous or determined attempt.
strenuous physical or mental exertion.
2. technical a force exerted by a machine or in a process.
Derivatives
effortful adjective
effortfully adverb
Origin
C15: from Fr., from OFr. esforcier, based on L. ex- 'out' + fortis 'strong'.

Wikipedia

Logical effort

The method of logical effort, a term coined by Ivan Sutherland and Bob Sproull in 1991, is a straightforward technique used to estimate delay in a CMOS circuit. Used properly, it can aid in selection of gates for a given function (including the number of stages necessary) and sizing gates to achieve the minimum delay possible for a circuit.